1. Field of the Invention
The present invention relates to a method for inspecting semiconductor devices, liquid crystals, and magnetic heads.
An example in which a semiconductor wafer is inspected will be explained.
2. Description of the Related Art
Semiconductor devices are manufactured by repeating a process that uses lithography or etching to transfer a pattern, usually formed on a photomask, onto a semiconductor wafer. In a semiconductor device manufacturing process, the quality of the lithography or etching, the quality of various other types of processing, and the production of foreign matter can greatly affect the semiconductor device yield. Therefore, methods for inspecting semiconductor wafers from a manufacturing process have conventionally been implemented to detect anomalies or faults early or before they occur.
Methods for inspecting for defects in patterns on semiconductor wafers involve the use of a defect inspection device that irradiates the semiconductor wafer with white light and uses the optical image to compare the same circuit patterns on a plurality of LSI. For example, as disclosed in Japanese Patent Laid-open H3-167456, in an inspection method that uses optical images, the optically illuminated area on a substrate is imaged on an integrated time delay sensor. Defects are detected by comparing the image detected by the sensor and design information already entered.
In the aforementioned defect inspection, adjoining identical circuit pattern images are formed. These images are then compared and defects automatically detected. However, inspections must also handle wafers that have various pattern layouts or patterns that involve various materials. To accurately compare adjoining patterns, the positioning of the pattern, that is the chip (die) and shot matrices on the wafer, must be predetermined and preset as inspection conditions for wafers to be inspected. In addition, to enable the formation of images suitable for inspection in various materials, appropriate values must be set for image brightness and the pattern-substrate contrast and these values preset as inspection conditions for wafers to be inspected. However, there are no descriptions of the procedures or operation methods for these inspection condition settings for the above conventional devices and their operation is complex, between one and several hours being required to set appropriate inspection conditions for a new wafer to be inspected. A problem exists in that, in order to implement pattern inspections for a plurality of products (that is a plurality of circuit pattern matrices) and a plurality of processes (that is a plurality of materials and a plurality of detailed circuit pattern forms) in a semiconductor manufacturing line, a huge number of inspection conditions must be set. As a result, an enormous amount of time is required in all inspection operations and in particular, in inspection condition setting operations.
Japanese Patent Laid-open 2001-35893 discloses a method for improving operation efficiency when the above inspection conditions are set and for reducing the time involved in setting inspection conditions. The design of the operation screen layout reduces the time needed for the entry of setting items but even so, between thirty minutes and several hours are required to set inspection conditions in the inspection device.
FIG. 1 is one conventional example of inspection condition settings and shows a conditions setting sequence for a foreign matter inspection device that uses scattered laser light. The conventional setting of inspection conditions starts with preparation of a wafer and loading of that wafer into the device. As preliminary preparation for inspection, the chip matrix within the wafer, the shot matrix when the pattern is exposed, the chip size, and test element group (TEG) chips for process and yield management must be set so that they will not be inspected and the direction of the wafer scan during the inspection and the chips to be used in alignment must be set. Furthermore, a pattern that uses automatic alignment is selected, the image data of the alignment pattern saved, and actual alignment implemented.
After the above settings are completed, adjustment of the inspection sensitivity starts. Firstly, an special filter that efficiently shields diffracted light from repetitive patterns on the chip is set. A trial inspection then takes place. The detection results are confirmed (reviewed) after the trial inspection and a temporary laser power value and threshold value, which are sensitivity conditions, are set. After repeating the sensitivity condition settings, trial ion and review, and then determining inspection conditions so that less than a certain percentage of false alarms occur, the inspection conditions are saved and the wafer unloaded. This ends the extraction of conditions.
In a device that inspects various types of intricate patterns including those on semiconductor devices as in the above description of conventional technology, various inspection conditions must be set and these conditions must be adjusted for each product and each process. The inspection device is occupied while conditions are being extracted, thus actually reducing inspection time. Also, because there are a plurality of entry items, a worker who sets conditions requires a certain amount of training and must be experienced in the use of the device. Furthermore, while conditions are being extracted, there is an accumulation of semiconductor products. Therefore, the turnaround time (TAT) of semiconductor devices is extended and costs increase.